Low Power-High Performance
Energy/bit optimization approach for multi-chip systems with possibility of co-optimization with the routing resources defined by the signalling pitch.
More than Moore technologies can be supported by system level diversification enabled by chiplet based integrated systems within multi-chip-modules (MCM) and silicon interposer based 2.5D systems. The division of large system-on-chip dies into smaller chiplets with different technology nodes specific to the chiplet application requirement enables the performance enhancement at system level while achieving lower power consumption. However, these chiplets need to communicate between each other. Routing resources in MCM and 2.5D systems are limited due to system size and thickness restrictions. This work presents energy/bit optimization approach for multi-chip systems with possibility of co-optimization with the routing resources defined by the signalling pitch. Holistic design methodologies are shown which can be further extended by the designer to define the application specific constraints. A detailed analysis of energy per bit relationship to the voltage swing requirement for different topologies is presented along with a specific CML signalling oriented design flow for 2.5D chip to chip interfaces as an example of topology specific optimization possibilities within this methodology. https://doi.org/10.1109/TCPMT.2021.3117118
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